DocumentCode
713029
Title
A review on performance comparison of SOI MOSFET with STS-SOI MOSFET
Author
Karthick, S. ; Ajayan, J. ; Vivek, K. ; Arasan, C. Kavin ; Manikandan, A.
Author_Institution
Dept. of ECE, MIT Pondicherry, Puducherry, India
fYear
2015
fDate
26-27 Feb. 2015
Firstpage
1401
Lastpage
1406
Abstract
The last few decades have seen considerable progress in development of techniques for growing single crystal silicon film on insulator (SOI) substrates suitable for the fabrication of high performance devices. The SOI substrates promise to extend the range of applications including VLSI, memory, analog and digital integrated circuits and mixed signal applications. In this paper, the performance of SOI technology based SOI MOSFETs and schottky tunneling source SOI MOSFETs is reviewed. The SOI technology along with metallic S/D offers several benefits that enable scaling to sub 22nm gate lengths including extremely low S/D parasitic resistances, superior control of leakage current and elimination of bipolar latch up action. STS-FETs also benefits from the use of high-k dielectrics along with S/D engineering and gate engineering.
Keywords
MOSFET; bipolar transistors; leakage currents; silicon-on-insulator; SOI MOSFET; bipolar latch up action; high-k dielectrics; leakage current; schottky tunneling source; single crystal silicon film on insulator substrates; CMOS integrated circuits; Logic gates; MOSFET; Metals; Silicides; Silicon-on-insulator; Erbium silicide; Schottky barriers (SBs); metal source/drain (S/D); platinum silicide;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics and Communication Systems (ICECS), 2015 2nd International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-7224-1
Type
conf
DOI
10.1109/ECS.2015.7124815
Filename
7124815
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