Power minimization for clustered routing in network on chip architectures

Traditional System-on-Chip (SoC) design employs shared buses for data transfer among various subsystems. As SoC becomes more complex involving a larger number of subsystems, traditional bus-based architecture is giving way to a new paradigm for on-chip communication. A communication network of point-to-point links and routing switches is used to facilitate communication between the subsystems. The considerations that have driven data communication from shared buses to packet-switching networks in clustered architectures (spatial reuse, multi-hop routing, flow and congestion control, and standard interfaces for design reuse, etc.) will inevitably drive VLSI designers to use these principles in on-chip interconnects.