DocumentCode :
713064
Title :
Design and verification of Ethernet, VME IP core using ACE and CDC
Author :
Preetam, Isukametla Neenu ; Mazumder, Pankaj ; Sai Kumar, T. ; Raghu Krishna, S. ; Kumawat, Renu
Author_Institution :
Dept. of ECE, Manipal Univ. Jaipur (MUJ), Jaipur, India
fYear :
2015
fDate :
26-27 Feb. 2015
Firstpage :
194
Lastpage :
198
Abstract :
In today´s verification field System-On-a-Chip (SOC) designs contain increased levels of functional and structural complexities. Different SOC´s having various design blocks and those blocks are operated at different clock frequencies which causes CDC issues. The CDC issues are visualized through ACE using Blue Pearl Software Suite. In this paper we discuss about Advance Clock Environment (ACE) and Clock Domain Crossing (CDC) using Blue Pearl Software Suite (BPS) of Ethernet and VME (Voice Modulation Engine) IP Core.
Keywords :
clocks; electronic design automation; local area networks; logic circuits; system-on-chip; ACE; BPS; Blue Pearl Software Suite; CDC issues; Ethernet; SOC designs; VME IP Core; advance clock environment; clock domain crossing; clock frequencies; system-on-a-chip designs; voice modulation engine; Clocks; Data transfer; IP networks; Software; Synchronization; System-on-chip; Visualization; ACE; BPS; CDC; Ethernet; VME;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics and Communication Systems (ICECS), 2015 2nd International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-7224-1
Type :
conf
DOI :
10.1109/ECS.2015.7124891
Filename :
7124891
Link To Document :
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