Design of efficient multiply-accumulate block for PID controllers

Proper closed loop has been an ever burning issue in many automotive industries. The industrial equipments which are governed by PID controllers have simple control structure and efficiency but still they suffer from large power consumption and slow mathematical computation. Many researchers have tried and are trying to design a low power, delay less PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers which in turn incorporated in PID architecture. The simulations are done in Modelsim and power results are synthesized using Xilinx ISE. The results suggest that Wallace tree based MAC unit consumes less power and area.