Performance evaluation of different allocation algorithms using FPGA platforms

The communication between processing elements are suffering challenges due to latency. The arbitration algorithm used inside an arbitration unit of a network-on-chip based router plays a significant role in determining the performance of the whole network-on-chip based mesh. This paper revaluates some of the standard forms of the arbitration algorithms and presents the synthesis and implementation on FPGA platforms. The work will help NoC designers to suitable allocation algorithms for their FPGA design The implementation is carried out using various arbitration algorithms responsible for scheduling 12-bit request vector. The implementation targets Virtex5 FPGA family. The analysis concludes that the iSlip allocation algorithm shows lower power delay product and lower resource utilization and a reasonably lower area delay product when implemented for speed optimization goal. Hence it can be best used for high speed low power NoC based systems.