Hardware implementation of a background substraction algorithm in FPGA-based platforms

Different strategies for the implementation of a fuzzy logic-based background subtraction algorithm are presented in this paper. The goal of this contribution is to obtain an efficient implementation suitable to be integrated into hardware platforms with limited resources. In order to find an adequate performance-resources trade-off, the design space is explored taken into account several strategies and implementation options. The final implementation is encapsulated within an IP core that has been used in a demonstrator, built on a Spartan-3A-DSP FPGA development board, suitable for processing VGA (640×480P) @ 60 Hz.