• DocumentCode
    713584
  • Title

    Test set embedding into hardware generated sequences using an embedding algorithm

  • Author

    Voyiatzis, I. ; Kavvadias, D. ; Sinitos, S. ; Vlahantonis, K. ; Kyrkos, P. ; Sgouropoulou, C. ; Efstathiou, C.

  • Author_Institution
    Dept. of Inf., Technol. Educ. Inst. of Athens, Athens, Greece
  • fYear
    2015
  • fDate
    21-23 April 2015
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this work an algorithm for embedding test sets containing don´t care values into sequences generated by binary counters is utilized and evaluated. Furthermore, a simple, yet effective, technique to decrease test application time is explored. Experiments carried out on ISCAS benchmarks reveal that the proposed scheme results in considerably shorter test sequences.
  • Keywords
    binary sequences; counting circuits; integrated circuit testing; ISCAS benchmark; binary counter; hardware generated sequence; test set embedding algorithm; Benchmark testing; Built-in self-test; Europe; Generators; Hardware; Informatics; Radiation detectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on
  • Conference_Location
    Naples
  • Type

    conf

  • DOI
    10.1109/DTIS.2015.7127346
  • Filename
    7127346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=713584