• DocumentCode
    713587
  • Title

    Scan-chain intra-cell defects grading

  • Author

    Touati, A. ; Bosio, A. ; Dilillo, L. ; Girard, P. ; Virazel, A. ; Bernardi, P. ; Reorda, M. Sonza

  • Author_Institution
    LIRMM, UM2, Montpellier, France
  • fYear
    2015
  • fDate
    21-23 April 2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell defect coverage affecting scan flip-flops. The experimental results show that a meaningful test solution has to be developed to improve the overall defect coverage for the scan chain testing.
  • Keywords
    automatic test pattern generation; flip-flops; ATPG test patterns; scan chain testing; scan flip-flops; scan-chain intracell defects grading; test quality; transistor size; Circuit faults; Databases; Flip-flops; Libraries; Logic testing; Multiplexing; fault simulation; intra-cell defect; scan-chain testing; test;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on
  • Conference_Location
    Naples
  • Type

    conf

  • DOI
    10.1109/DTIS.2015.7127349
  • Filename
    7127349