Multi-valued logic test access mechanism for test time and power reduction

Test time reduction is an important objective in SoC testing. This becomes harder to achieve when power management techniques, like dynamic voltage scaling, are used, that requires a core to be tested for all its operating voltages. Coupling test time with test power consumption, due to long interconnects and switching power consumption, creates a difficult situation for SoC testing. To cope with this issue, this paper proposes a new Test Access Mechanism (TAM) that uses Multi-Valued Logic (MVL). In this structure, test data going to cores with MVL technique through the same test bus. This paper proposes Binary-MVL converters, and structure of test data on a multi-voltage test bus. This arrangement also reduces test time in multi-VDD SoCs as well. We have analyzed on crosstalk noise, area and power overhead of the proposed structure. In addition, we use IEEE 1450 - Standard Test Interface Language (STIL) to send and receive MVL signal in the Automatic Test Equipment (ATE) side. We also present a Mixed-Integer Linear Programming (MILP) model for optimal test scheduling based on our new TAM structure. Experimental results for ITC´02 benchmark highlight the effectiveness of the proposed structure.