• DocumentCode
    713595
  • Title

    Supply voltage variation impact on Anderson PUF quality

  • Author

    Barbareschi, Mario ; Bagnasco, Pierpaolo ; Mazzeo, Antonino

  • Author_Institution
    Dept. of Electr. Eng. & Inf. Technol., Univ. of Naples “Federico II”, Naples, Italy
  • fYear
    2015
  • fDate
    21-23 April 2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Physically Unclonable Function (PUF) is a promising technique to enhance the security of Integrated Circuits (ICs) by providing a challenge/response pairs (CRPs) set, generated from physical properties of the device in which it is embedded. Indeed PUFs exploit small random manufacturing process variations, mainly measuring delays, to extract responses, such that they are unique and unclonable. Since PUFs are not deterministic circuits until to their realization, the test for a PUF is a process which involves statistical evaluation of some features, such as uniformity and reliability. The former measures the bits biasing for PUFs responses. The latter is related to the PUFs robustness against external uncontrolled disturbances (e.g. voltage variations), which could affect responses stability. Therefore, in this paper, we demonstrate the impact of the voltage variation on the Anderson PUF, implemented on the Xilinx Spartan-3E family. In particular, through experimental results, we show that the supplied voltage value is able to dramatically change the quality of Anderson PUF responses.
  • Keywords
    industrial property; integrated circuit manufacture; integrated circuit measurement; integrated circuit reliability; Anderson PUF quality; CRP set; Xilinx Spartan-3E family; challenge/response pairs set; external uncontrolled disturbances; integrated circuits security; measuring delays; physically unclonable function; supply voltage variation; Delays; Field programmable gate arrays; Multiplexing; Stability analysis; Threshold voltage; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on
  • Conference_Location
    Naples
  • Type

    conf

  • DOI
    10.1109/DTIS.2015.7127361
  • Filename
    7127361