Modeling avalanche breakdown for ESD diodes in integrated circuits

Usually device compact models do not include breakdown mechanisms which are fundamental for ESD protection devices. This work proposes a novel spice-compatible modeling of breakdown phenomena for ESD diodes. The developed physics based approach includes minority carriers propagation and can be embedded in the simulation of parasitic substrate noise of power devices. The model implemented in VerilogA has been validated with device simulations for a simple structure at different temperatures showing good agreement and robust convergence.