Application-specific power-aware mapping for reconfigurable NoC architectures

In this paper, we propose a new topology-core reconfigurable architecture for network-on-chips (NoC). The majority of existing research on reconfigurable architectures is focused on either reconfiguring topology of NoC or reconfiguring processing elements of the network. Our approach uses a hybrid algorithm to take advantages of both these methods by using field programmable gate array (FPGA) as reconfigurable processing elements. Moreover, programmable switches among routers are applied for topology reconfigurability. The experimental results show extensive improvement over the state-of-the-art research in terms of power consumption, network performance and application execution time.