DocumentCode :
714042
Title :
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget
Author :
Sengupta, Anirban ; Sedaghat, Reza
Author_Institution :
Comput. Sci. & Eng., Indian Inst. of Technol., Indore, Indore, India
fYear :
2015
fDate :
3-6 May 2015
Firstpage :
69
Lastpage :
74
Abstract :
Detecting error or producing correct output is the primary function of a fault secured system. In the context of multi-cycle transient faults, design space exploration (DSE) of an optimal fault secured datapath based on user constraints of area and delay during high level synthesis (HLS) is considered notorious. This is derived from the fact that generation of a user budget bounded multi-cycle transient fault secured datapath may not be possible for every type of candidate design solution produced during exploration. Additionally, insertion of inapt cut to optimize delay overhead associated with fault security in most cases may not yield optimal solutions in the context of user constraints/budgets. This paper resolves the above problems which has not been addressed in the literature so far by proposing the following novelties: (a) fault secured particle swarm optimization (PSO) driven DSE methodology (b) Techniques to handle multi-cycle transient faults during DSE (c) Schemes for choosing pertinent edges for inserting cut (s) in scheduled Control Data Flow Graph (CDFG) that optimizes the delay overhead associated with fault security. Results of the proposed approach indicated that the fault secured solution found comprehensively minimizes the final cost as well as satisfies the conflicting user budgets. Further, the final fault secured solution yielded is significantly lower in cost compared to solutions obtained through recent similar approaches.
Keywords :
data flow graphs; fault diagnosis; particle swarm optimisation; power system security; CDFG; DSE methodology; HLS; PSO; candidate design solution; design space exploration; high level synthesis; optimal multicycle transient fault secured datapath; particle swarm optimization; scheduled control data flow graph; user area-delay budget; user budgets; user constraints; Circuit faults; Convergence; Delays; Hardware; Resource management; Security; Transient analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering (CCECE), 2015 IEEE 28th Canadian Conference on
Conference_Location :
Halifax, NS
ISSN :
0840-7789
Print_ISBN :
978-1-4799-5827-6
Type :
conf
DOI :
10.1109/CCECE.2015.7129162
Filename :
7129162
Link To Document :
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