Enhanced placement algorithm for FPGAs using sparse circuit

To improve the efficiency of logic block placement in Field Programmable Gate Array (FPGA) design flow a new enhancement technique is proposed which is realized as a part of simulated annealing optimization method. Searching in placement space is done faster and more efficiently using a simplified version of the target circuit called Sparse Circuit. Some of the pitfalls that may happen in a random initial placement of the circuit are discussed and suggestions are proposed to improve the duration and quality of placement.