Efficiency optimization for monolithic step-up dc-dc converters

This paper presents an algorithm for optimizing the conversion efficiency of monolithic step-up dc-dc converters. The algorithm starts from the technology parameters and design specifications considering the tradeoff between the inductance and the series parasitic resistance. After specifying the area and the frequency of a planar spiral inductor, the algorithm maximizes the inductance and minimizes the parasitic resistance. Upon specifying the step-up dc-dc converter parameters, the algorithm finds the maximum possible efficiency. The procedure can be applied to on-chip and on-board planar inductors. A practical example is also presented to elaborate on the steps of applying the optimization algorithm.