Title :
CS-based TIAs using inductive feedback approach in 90nm CMOS
Author :
Ghasemi, Omidreza
Author_Institution :
ECE Dept., Concordia Univ., Montreal, QC, Canada
Abstract :
In this paper, inductive feedback approach is applied for bandwidth extension of Common Source Transimpedance Amplifier. The effect of parasitic capacitances of the MOS transistor is reduced using this approach. The process of zero-pole cancellation for extending the bandwidth of the amplifier is explained. Moreover, a wideband three stage transimpedance amplifier based on common source amplifier is introduced. To demonstrate the feasibility of the technique, the transimpedance amplifiers are simulated in a well-known CMOS technology (i.e. 90nm STMicroelectronics). The single stage amplifier achieves 3-dB bandwidths of 32.1GHz, in the presence of a 50fF photodiode capacitances and 5fF loading capacitance while only dissipating 2.03mW. The three stage amplifier achieves bandwidths of 42.8GHz in the presence of 50fF photodiode capacitance and 5fF loading capacitance. The power consumption for the 3-stage transimpedance amplifier is 6.1mW. For all the structures noise performance is competitive in comparison with other works. Eye diagram evaluation for each topology shows the capability of the technique to pass high data rate effectively without inter symbol interference.
Keywords :
CMOS analogue integrated circuits; MIMIC; MOSFET; microwave photonics; operational amplifiers; photodiodes; wideband amplifiers; CMOS technology; CS-based TIA; MOS transistor; STMicroelectronics; amplifier bandwidth extension; bandwidth 32.1 GHz; bandwidth 42.8 GHz; bandwidth extension; capacitance 5 fF; capacitance 50 fF; common source amplifier; common source transimpedance amplifier; eye diagram evaluation; inductive feedback approach; loading capacitance; noise performance; parasitic capacitance effect; photodiode capacitance; power 2.03 mW; power 6.1 mW; power consumption; single-stage amplifier; size 90 nm; wideband three-stage transimpedance amplifier; zero-pole cancellation process; Bandwidth; CMOS integrated circuits; Capacitance; Inductors; Integrated circuit modeling; Noise; Poles and zeros;
Conference_Titel :
Electrical and Computer Engineering (CCECE), 2015 IEEE 28th Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
978-1-4799-5827-6
DOI :
10.1109/CCECE.2015.7129439