Efficient Global Back-Projection on an FPGA

The Global Back-Projection (GBP) Algorithm has been known for use in Synthetic Aperture Radar (SAR) image formation for many years. But, despite many advantages compared to other algorithms, GBP usage is limited. It requires significant computational complexity and consumes more power. This paper presents a high-performance architecture which allows efficient and scalable implementation of the GBP algorithm on a Field Programmable Gate Array (FPGA). Such an architecture is based on a systolic array that performs back-projection in a pipelined way, using parallelism over image pixels and radar pulses. A GBP systolic array is built using specially designed back-projection streaming cores. The cores utilize a floating-point calculation on the FPGA to achieve accurate and high-dynamic range in GBP integration. Results presented herein, show the achieved performance of GBP-based image formation using an FPGA and details the power consumption of the described implementation. Comparison is made to other computational platforms in order to determine advantage for real-time and power constrained SAR applications and platforms.