ESD reliability comparison of different layout topologies in the 0.25-μm 60-V nLDMOS power devices

The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (V_t1), holding voltage (V_h) and secondary breakdown current (I_t2). Eventually, it can be found that how to sketch the layout pattern of an nLDMOS is a very important issue in the anti-ESD consideration. The waffle-type nLDMOS DUT is poor contribution to I_t2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the I_t2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared with a traditional striped-type (reference) nLDMOS device. The ESD abilities of traditional striped-type and waffle-type nLDMOS devices with an embedded SCR (pnp-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR (pnp-manner arrangement) is a good structure for the anti-ESD reliability in high-voltage applications.