Title :
Evaluation of electrical performance of various tunnel TFETs
Author :
Chi Huang ; Tao-Yi Hung ; Pei-Yu Wang ; Bing-Yue Tsui
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.
Keywords :
field effect transistors; semiconductor device models; tunnel transistors; TFET; circuit delay; parasitic capacitances; power dissipation; subthreshold swing; tunnel field-effect transistor; ultralow power applications; Logic gates; Parasitic capacitance; Semiconductor process modeling; Silicon; Tunneling; parasitic capacitance; subthreshold swing; tunnel field-effect transistor;
Conference_Titel :
Next-Generation Electronics (ISNE), 2015 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/ISNE.2015.7132032
