DocumentCode
715496
Title
Polar codes for magnetic recording channels
Author
Bhatia, Aman ; Taranalli, Veeresh ; Siegel, Paul H. ; Dahandeh, Shafa ; Krishnan, Anantha Raman ; Lee, Patrick ; Dahua Qin ; Sharma, Moni ; Teik Yeo
Author_Institution
Univ. of California, San Diego, La Jolla, CA, USA
fYear
2015
fDate
April 26 2015-May 1 2015
Firstpage
1
Lastpage
5
Abstract
Polar codes provably achieve the capacity of binary memoryless symmetric (BMS) channels with low complexity encoding and decoding algorithms, and their finite-length performance on these channels, when combined with suitable decoding algorithms (such as list decoding) and code modifications (such as a concatenated CRC code), has been shown in simulation to be competitive with that of LDPC codes. However, magnetic recording channels are generally modeled as binary-input intersymbol interference (ISI) channels, and the design of polar coding schemes for these channels remains an important open problem. Current magnetic hard disk drives use LDPC codes incorporated into a turbo-equalization (TE) architecture that combines a soft-output channel detector with a soft-input, soft-output sum-product algorithm (SPA) decoder. An interleaved coding scheme with a multistage decoding (MSD) architecture with LDPC codes as component codes has been proposed as an alternative to TE for ISI channels. In this work, we investigate the use of polar codes as component codes in the TE and MSD architectures. It is shown that the achievable rate of the MSD scheme converges to the symmetric information rate of the ISI channel when the number of interleaves is large. Simulations results comparing the performance of LDPC codes and polar codes in TE and MSD architectures are presented.
Keywords
decoding; interleaved codes; intersymbol interference; parity check codes; ISI channels; LDPC codes; MSD architectures; TE; binary memoryless symmetric channels; binary-input intersymbol interference channels; code modifications; decoding algorithms; interleaved coding scheme; magnetic recording channels; multistage decoding architecture; polar codes; soft-input soft-output sum-product algorithm decoder; turbo-equalization architecture; Bit error rate; Decoding; Encoding; Magnetic recording; Memoryless systems; Parity check codes; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory Workshop (ITW), 2015 IEEE
Conference_Location
Jerusalem
Print_ISBN
978-1-4799-5524-4
Type
conf
DOI
10.1109/ITW.2015.7133166
Filename
7133166
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