High frequency jitter estimator for SoCs

This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the under-sampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in high-volume by ST Microelectronics.