Title :
A compact, high-gain Q-band stacked power amplifier in 45nm SOI CMOS with 19.2dBm Psat and 19% PAE
Author :
Wei Tai ; Ricketts, David S.
Author_Institution :
ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
We present a compact, high-gain power amplifier (PA) that achieves high power and high output impedance through a 4-stacked architecture. By proper adjustment of device sizes and bias voltages, the optimum load impedance for maximum Psat is moved close to 50Ohm which eliminates the need for an output matching network. The single-stage PA exhibits a high gain of 16 dB which is more than twice the gain of previously reported PAs and 19.2dBm Psat and 19% PAE which are comparable to the state-of-the-art CMOS PAs at Q-band. The very compact area of 0.09 mm2 and the high gain makes this design a suitable unit PA to be used for further parallel power combining to reach Watt levels of output power.
Keywords :
CMOS analogue integrated circuits; field effect MIMIC; millimetre wave power amplifiers; silicon-on-insulator; 4-stacked architecture; Q-band; SOI CMOS PAs; bias voltages; compact high-gain Q-band stacked power amplifier; device sizes; efficiency 19 percent; optimum load impedance; output matching network; parallel power combining; single-stage PA; size 45 nm; CMOS integrated circuits; Gain; Impedance; Logic gates; Power generation; Radio frequency; Semiconductor device measurement;
Conference_Titel :
Power Amplifiers for Wireless and Radio Applications (PAWR), 2015 IEEE Topical Conference on
Conference_Location :
San Diego, CA
DOI :
10.1109/PAWR.2015.7139204
