Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations

This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CADENCE tool). The method is validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separate-well designs). These methodologies have been validated in the case of 1000 inverters chain and for heavy ions and demonstrate the impact of the quenching effect. Furthermore, both the designs were considered and the analyses are consistent with experiments and this allows for identification of the quenching effect as the main mechanism responsible for the difference in SET sensitivity. However, the modeling approach can be also used for other logical cells or/and complex radiation environments, to determine SET cross sections, SET cartographies and SET characteristics. This method is applied to SEU analyses, i.e., SBU (Single Bit Upset) and MCU (Multiple Cell Upset) for 65-nm bulk SRAM memory and neutron/proton SET modeling.