A new ultra low power high speed dynamic comparator

High speed, low voltage circuits are widely used today, e.g. bio-implantable circuits and ADCs. Comparators are considered as base block for analog to digital convertors. The comparator circuit with preamplifier increase the power dissipation. This is pushing toward dynamic regenerative comparators to improve this problem. In this paper we have used cross coupled mechanism to improve dynamic operation of the comparator. Also we have analyzed dynamic comparator´s delay time. A new circuit with high speed, very low power consumption, very short delay time and very low voltage is proposed. Simulation results in a 90-nm CMOS technology confirm the analysis result. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3 GHz while consuming only 6 nW of power and with 79 ps delay time.