Design of a new split-capacitive-array DAC based on distribution of attenuation capacitor

In this paper, a new split capacitive array digital to analog converter (DAC) with the advantage of capacitor area reduction is presented. In more details, the attenuation capacitor of the conventional split array DAC is distributed to achieve small integral nonlinearity (INL) and differential nonlinearity (DNL) errors, low glitch energy, small capacitor mismatches, high speed and small chip area. To compare this work with conventional structures, an 8-bit DAC with the proposed configuration in 0.18μm CMOS technology is designed. Simulation results show that 47% reduction in the value of capacitors is achieved and spurious-free dynamic range (SFDR) of the proposed configuration at 40 MS/s is 6 dB better than the conventional structure for various frequencies of sinusoidal input signal. In addition, total power consumption of the designed DAC is 760 μWatt and more accurate operation is obtained.