Methods of logical synthesis for library elements and blocks with regular layout structure

The paper is devoted to research and development of custom IP-blocks design methods in the form of standard elements with regular layout structure in the layers of polysilicon and diffusion. For today the leading developers of microelectronic devices continue to work out the key modules of microelectronic systems, such as core microprocessors, microcontrollers completely custom-made in a mode in which the final composition of library elements is not known beforehand, and the design is extremely low at the transistor level. However, automation of logic and layout synthesis process for a completely custom design is difficult due to significant increase in the complexity of the problem with increasing integration of microelectronic systems and decreasing the size of the standard elements to 22nm and below. The authors proposed FinFET layout design formation methods for layout synthesis of elements with a regular layout structure in layers of polysilicon and diffusion.