Title :
Verification of timed Finite State Machines
Author :
Kidyarova, Galina ; Yevtushenko, Nina
Author_Institution :
Tomsk State Univ., Tomsk, Russia
Abstract :
In this paper, a method is proposed for checking whether two timed Finite State Machines (TFSMs) are equivalent. In the second part of the paper, TFSMs are represented as logic circuits and correspondingly, the verification problem is reduced to their scalable representations where the SAT-solving problem can be efficiently used.
Keywords :
finite state machines; logic circuits; SAT-solving problem; TFSM; logic circuit; timed finite state machine; verification problem; Automata; Boolean functions; Combinational circuits; Delay effects; Delays; Sequential circuits; SAT-solving; logic circuit; timed Finite State Machine; verification;
Conference_Titel :
Control and Communications (SIBCON), 2015 International Siberian Conference on
Conference_Location :
Omsk
Print_ISBN :
978-1-4799-7102-2
DOI :
10.1109/SIBCON.2015.7147095
