At-Speed Path Delay Test

This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any other structural test technique. The path generation algorithm uses the circuit structure, and then the paths are sequentially justified using Boolean Satisfiability algorithms.