SoC TAM Design to Minimize Test Application Time

We propose a new test access mechanism(TAM) design to reduce the System-on-chip (SoC) test application time (TAT) under various hardware and power constraints. Prior works on TAM design focus on designing TAM architecture based on fixed cores parameters, which assumes unchanged internal scan chains and layout arrangement of cores, and therefore is unable to make effective use of SoC resources for testing purpose. Moreover, previous works on SoC test scheduling fail to incorporate the presented hardware and power constraints at once, which may render the testing result inapplicable. The proposed TAM design is tightly integrated with scan chain redesign and layout arrangement of individual core in SoC, and thus able to reduce the wiring complexity and to make effective use of TAM resources. Various hardware and power constraints are considered in this work, which are often ignored or partly addressed by previous SoC test scheduling work. Dynamic voltage and frequency scaling (DVFS) is adopted in test scheduling to minimize testing time. Both session-less and session-based scheduling are formulated in Mixed-integer linear programming. Experimental result of a set of ITC´02 benchmark shows up to 69% of reduction in test application time with the proposed TAM Design and DVFS scheduling.