PFAL based power efficient mux based decoder

Author

Aron, Sonal ; Garg, Shelly ; Niranjan, Vandana

Author_Institution

Dept. of ECE, IGDTUW, New Delhi, India

fYear

2015

fDate

15-16 May 2015

Firstpage

1010

Lastpage

1013

Abstract

Low power circuit techniques have become indispensable need of the hour for VLSI design. One such low power technique which has gained popularity over the past decade is adiabatic technique. It is based on the concept of reusability of power. In this paper, a positive feedback adiabatic logic (PFAL) based mux decoder is proposed. The decoder has been designed in 180nm CMOS technology and simulated using SPICE. The PFAL based decoder outperforms the conventional CMOS based decoder in terms of power dissipation. A significant reduction of 41.867% in power dissipation has been achieved in the proposed mux decoder.

Keywords

CMOS integrated circuits; VLSI; logic circuits; low-power electronics; CMOS technology; PFAL; SPICE; VLSI design; adiabatic technique; low power circuit; positive feedback adiabatic logic; power dissipation; power efficient mux based decoder; power reusability; size 180 nm; Binary codes; CMOS integrated circuits; CMOS technology; Decoding; Multiplexing; Power dissipation; Very large scale integration; PFAL; adiabatic; flash ADC; low power; mux based decoder; power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communication & Automation (ICCCA), 2015 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-8889-1

Type

conf

DOI

10.1109/CCAA.2015.7148523

Filename

7148523