Performance comparison of pass transistor and CMOS logic configuration based de-multiplexers

This research paper analyzes the performance of De-Multiplexer (De-Mux) using Pass Transistor Logic Configuration (PTLC) and CMOS Logic Configuration (CLC). Furthermore, a comparison between the performances of both the configurations in terms of power dissipation, chip area, power supply and drive current levels are analyzed. Besides this, paper also signifies more than 50% decrement in interconnect lengths, chip area and number of transistors count while using pass transistor logic configuration in comparison to 1:2 De-Mux implemented with CMOS logic configuration. Moreover, reduction in supply voltage and decrement in power dissipation up to 70% is observed in pass transistor logic comparing to CMOS logic.