A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability

Author

Do, Nhan ; Tee, Latt ; Hariharan, Santosh ; Lemke, Steven ; Tadayoni, Mandana ; Will Yang ; Mt Wu ; Jinho Kim ; Yueh-Hsin Chen ; Chien-Sheng Su ; Tiwari, Vipin ; Zhou, Stephen ; Qian, Rodger ; Yue, Ian

Author_Institution

A Subsidiary of Microchip Technol. Inc., Silicon Storage Technol., Inc., San Jose, CA, USA

fYear

2015

fDate

17-20 May 2015

Firstpage

1

Lastpage

3

Abstract

In this paper, a Flash macro designed with high-density arrays of split-gate (SG) SuperFlash® cells, compatibly embedded in a 55 nm Low Power (LP) logic process is demonstrated with full functionality and excellent reliability at automotive temperature range. This split-gate Flash memory technology can be seamlessly and universally embedded in multiple logic process platforms, and can continually be scaled to 40 nm and smaller lithographically nodes, without compromising performance and reliability.

Keywords

automotive electronics; flash memories; integrated circuit design; integrated circuit reliability; integrated logic circuits; logic arrays; low-power electronics; LP logic process; SG SuperFlash cells; automotive temperature; high access speed; high-density arrays; lithographically nodes; logic-process-compatible split-gate flash memory array; low power logic process; multiple logic process platforms; reliability; size 40 nm; size 55 nm; Arrays; Automotive engineering; Logic gates; Nonvolatile memory; Reliability; Split gate flash memory cells; Temperature distribution;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2015 IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4673-6931-2

Type

conf

DOI

10.1109/IMW.2015.7150267

Filename

7150267