DocumentCode
719540
Title
Junction Optimization for Embedded 40nm FN/FN Flash Memory
Author
Baiano, Alessandro ; van Duuren, Michiel ; van der Vegt, Erik ; Schippers, Bob ; Beurze, Robert ; Tajari Mofrad, Daniel ; van Zwol, Hans ; Yu Chen ; Chiang, Jed ; Lokker, Han ; van Dijk, Kitty ; Verbree, Jouke ; Yi Ning Chen ; Garbe, Jochen ; Verhaar, Rob
Author_Institution
NXP Semicond., Nijmegen, Netherlands
fYear
2015
fDate
17-20 May 2015
Firstpage
1
Lastpage
4
Abstract
2-transistor (2T) cell technology used for embedded non-volatile memory (eNVM) has been scaled down to 40nm node. To enable aggressive cell scaling, the array architecture is modified compared to previous generations and the channel length of cell is drastically reduced requiring steep cell junctions, which give rise to new disturb phenomena. This paper describes how to safeguard the drain disturb immunity in 40nm 2T eNVM, while maintaining the intrinsic 2T robustness.
Keywords
flash memories; logic design; random-access storage; 2-transistor cell technology; embedded FN/FN flash memory; embedded non-volatile memory; junction optimization; size 40 nm; Arrays; Junctions; Microprocessors; Optimization; Programming; Temperature measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2015 IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4673-6931-2
Type
conf
DOI
10.1109/IMW.2015.7150292
Filename
7150292
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