Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures

This paper presents the design of high speed multiplier and squaring architectures based upon ancient Indian Vedic mathematics sutras. In existing Vedic multiplier architectures, the partial product terms are computed in parallel and then added at the end to get the final result. In this work, all the partial products are adjusted using concatenation operation and are added using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squaring modules. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only, the designed multiplier offers significant improvement in speed. The designed architectures are realized using Xilinx Spartan-3E FPGA. The comparison shows the 28.72% and 38.59% reduction in propagation delay for the designed 32-bit multiplier as compared to the existing multiplier designs.