Crossing register transfer level for VLSI circuits

This paper presents an efficient automatic test pattern generation paradigm to gain confidence in the correctness of designs of circuits. The paradigm is based on selection of a goal node determined by applying basic graph traversal on a graph model of a circuit under test and validation of a path passing through the goal node. The set of test patterns for the paths through a goal node suffices to certify the correctness of a design of a circuit under test. The derived set of test patterns can further be input to measure the percentage of correctness of the design. A subset of single clock circuits are dealt with to establish scalability and adaptability features of the proposed paradigm. The experimental result shows the effectiveness of the proposed test pattern generation scheme.