A common platform for bridging pre- and post-silicon verification in mixed-signal designs

The steadily increasing complexity of integrated circuits raises the burden on verification engineers of sophisticated System on Chips (SoCs). Simulations and formal verification alone are not able to detect all problems in a design due to unforeseen interactions between modules. These problems may occur even if the modules are logically independent from each other due to physical effects. Bugs found in post-silicon verification in the laboratory on the other hand need to be investigated and fixed with the help of design engineers. Therefore, collaboration between pre- and post-silicon verification is mandatory, which also allows to exploit synergies. Unfortunately, many environments currently in use handle these activities almost in complete separation, which complicates cooperations. This paper introduces a new approach to improve the situation by using a common test description language for pre- and post-silicon verification. It allows to describe test cases to be run in simulation as well as in physical post-silicon environments.