The optimazation method of device mismatch on 40 nm process technogy

Device parameter mismatch is considered as one of the major obstacle for continuing MOS transistor miniaturization following Moore´s law. As an efficient and accurate doping technique, ion implantation technology is an essential instrument for designing device parameter. This paper summarizes the device mismatch root causes and reviews some research results from the previous works. Device mismatch test layout structures and test condition are described. Finally we demonstrate that cold carbon implant has an obvious effect on optimizing device mismatch during LDD formation.