28 nm poly-cut layer lithography process developments

The paper presents the results of poly-cut layer lithography process development for 28 nm technology nodes and beyond, which include the simulation of illumination modes, the assessment of tri-layer chemical materials and verification on the silicon wafer. The small sigma illumination mode is considered as the most suitable illumination mode to meet the requirements of resolution and DOF performance of poly-cut layer based on simulation results. The best candidate of tri-layer materials is determined in view of the planarization and trench-filling performance as well as the capabilities of improving performance of pattern profile. The process window of ploy-cut layer is verified on silicon wafer on the basis of the optimum experiment conditions including illumination condition and tri-layer materials or others. Based on these results, we are able to obtain the excellent poly pattern in short length without shrinking line ends.