Method of improving enhance alignment quality in Double Patterning with Spacer process for 14–16nm FinFET

It is well known that different alignment mark designs will have different responses to process conditions. An Alignment mark optimized for traditional process might not be suitable for DPS (Double Patterning with Spacer) technology due to changes in lithography and etching process conditions^[1]. This paper characterized the influence of DPS Process of 14-16nm FinFET on the traditional ASML alignment mark, and different type of sub-segmentations within various types of ASML alignment marks (SPM53/SPM74/VSPM) were carried out to enable the alignment and find out the best performance of the alignment marks for DPS process. The design of the "H" type and "V" type sub-segmentations within the alignment marks is aimed to enhance the alignment signal strength and mark detectability. We also check different Fin-Etch process and zero layer mark impact on alignment signal. Alignment indicators of WQ (Wafer Quality) and ROP(Residual Overlay Perfonnance ) were used to judge the alignment performance and stability. A good correlation was established between sub-segmentations and wafer alignment signal strength.