Hard mask profile and loading issue study in SADP process

Author

Ermin Chong ; YiZheng Zhu ; ChunYan Yi ; Xianguo Dong ; Liang Zhang ; Quanbo Li ; Jun Huang ; Yu Zhang

Author_Institution

Shanghai Huali Microelectron. Corp., Shanghai, China

fYear

2015

fDate

15-16 March 2015

Firstpage

1

Lastpage

3

Abstract

Double Patterning (DP) technique is developed and applied to 45nm technology node and beyond by improving litho equipment and process windows. In addition in the 14/16nm node, the planar device is replaced by 3D FINFET architecture for device performance improvement; the SADP (self-align double patterning) technique is developed for FIN formation with focus on the smaller CD and LER (line edge roughness) evolution. The challenges during process development are FIN profile loading, core film profile tuning and others. In this paper, the authors introduce FIN formation and the main challenges during process development.

Keywords

MOSFET; lithography; masks; nanopatterning; 3D FINFET; FIN formation; FIN profile loading; LER; SADP process; core film profile tuning; hard mask profile; line edge roughness; litho equipment; loading issue; planar device; process window; self-align double patterning technique; size 45 nm; Films; Loading; Logic gates; Plasmas; Process control; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Technology International Conference (CSTIC), 2015 China

Conference_Location

Shanghai

ISSN

2158-2297

Type

conf

DOI

10.1109/CSTIC.2015.7153372

Filename

7153372