DocumentCode :
720821
Title :
Study of fin CD controllability for FinFET manufacturing
Author :
Hai Zhao ; Gang Mao ; Yang, Rex
Author_Institution :
Logic Technol. & Dev. Center, SMIC, Shanghai, China
fYear :
2015
fDate :
15-16 March 2015
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, several steps which would affect CD variation or Fin CD loss were analyzed during FinFET manufacturing, and then we figured out the dominant ones causing CD loss. Finally, an optimization guideline for Fin CD control in process integration was suggested for better Fin CD controllability. It´s not only good for Fin CD control, but also good for wide process margin to integrate smaller Fin CD beyond 20nm technology node.
Keywords :
MOSFET; optimisation; process control; semiconductor device manufacture; FinFET manufacturing; fin CD controllability; process integration; wide process margin; Annealing; FinFETs; Industries; Logic gates; Mass production; Performance evaluation; Surface treatment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Technology International Conference (CSTIC), 2015 China
Conference_Location :
Shanghai
ISSN :
2158-2297
Type :
conf
DOI :
10.1109/CSTIC.2015.7153428
Filename :
7153428
Link To Document :
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