DocumentCode
720831
Title
An empirical study of quality improvement on SiP assembly issue
Author
Ye, Samuel ; Kai Chang ; Dan Su ; Yu Lei ; Kungang Wang
Author_Institution
Availink Inc., Beijing, China
fYear
2015
fDate
15-16 March 2015
Firstpage
1
Lastpage
3
Abstract
This paper provides empirical evidence of fast root cause identification in assembly house for a case in which SiP chip wire bond showed high ratio of quality and reliability escapes. The identification has been performed through FMEA with a large number of RMAs and through quality control to rescreen goods called-back to minimize the field risk by using reliability tests. Furthermore, as a corrective action, authors have been working with major assembly house to implement a set of critical quality gates to improve the quality control in the wire bond process and management.
Keywords
failure analysis; integrated circuit reliability; lead bonding; quality control; system-in-package; FMEA; RMA; SIP assembly issue; SIP chip wire bond process; critical quality gate; failure mode and effects analysis; quality control; quality improvement; reliability test; system-in-package; Assembly; Moisture; Production; Reliability; SDRAM; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Technology International Conference (CSTIC), 2015 China
Conference_Location
Shanghai
ISSN
2158-2297
Type
conf
DOI
10.1109/CSTIC.2015.7153441
Filename
7153441
Link To Document