Sample preparation and improvement for Die Pull test

With the new BEOL scheme or package technology introduced, the chip and package interaction effect gets more and more concerns and focuses especially for most advanced technologies. To well reflect the impacts of these effects on the real product application performance, a new method of die pull (DP) test is proposed to evaluate the chip internal layer performance for a semiconductor device after back-grinding and die saw. Sample preparation flow, how to get a high successful rate and the failure modes analysis are introduced. Failure modes of DP are studied and robustness of different process splits is evaluated based on DP test. Delamination is not allowed to occur exclusively within Mx (IC) layers after Die Pull test. Process robustness can be judged with much shorter time comparing to traditional environment test. DP test is becoming an important methodology to evaluate the product robustness.