Platform level design for Network on Chips

As technology improves, it is possible to integrate more number of transistors on a single die, which means it is possible to design any complex system on single chip. The networking in such system is very difficult as compared to less complex systems one which uses switching and bus technique. In order to overcome this, a special networking technique is used which is Network on Chip. In this paper, a technique is proposed to develop the platform level design to receive the error-free packets which improves the performance of Network on Chip. By receiving the error free packets, there is no need for the network to check the packet once again for correctness thereby reducing the time taken for the packet to reach from source to destination resulting in an increase in efficiency. This helps in improving the performance since the error packet will be eliminated at the platform level before sending it to the cluster level. The packets are stored into RAM and are classified with the help of packet classifier. The packet classifier will send the packets to respective cluster and node agents at lower hierarchical level. This will improve the performance by avoiding the erroneous packets in network.