Title :
Design of Vedic multiplier for high fault coverage and comparative analysis with conventional multipliers
Author :
Gujamagadi, Pavan ; Sankolli, Pramod R. ; Kumar V, Praveen ; Nayak B, Raghavendra ; Palecha, Namita ; Suma, M.S.
Author_Institution :
Dept. of Electron. & Commun., RV Coll. of Eng., Bangalore, India
Abstract :
Multipliers are the major contributors to the overall throughput in most SoCs. Vedic arithmetic is a novel and simplified approach to perform complex operations. Any good design must be targeted for optimal Speed-Area Trade-off. Commercial application demands reliable and economical design which makes testability an important parameter. Stuck-at-fault model for the design is to be developed and proper metrics have to be used to measure testability. Good design implies high fault coverage also. In this paper, design of Vedic multiplier with high fault coverage is proposed. Vedic multiplier designed using Urdhva-Triyagbhyam Sutra operates faster than the conventional multipliers like Booth and Array multipliers. Comparative analysis of VLSI parameters such as throughput, area and fault coverage is done with other multipliers.
Keywords :
VLSI; logic design; multiplying circuits; system-on-chip; SoC; Urdhva-Triyagbhyam Sutra; VLSI parameter; Vedic multiplier; array multiplier; booth multiplier; comparative analysis; conventional multiplier; high fault coverage; speed-area trade-off; stuck-at-fault model; testability; Arrays; Automatic test pattern generation; Circuit faults; Conferences; Delays; Reliability; System-on-chip; Fault Coverage; Speed-Area Trade-off; Stuck-at-fault; Urdhva-Triyagbhyam Sutra; Vedic arithmetic;
Conference_Titel :
Advance Computing Conference (IACC), 2015 IEEE International
Conference_Location :
Banglore
Print_ISBN :
978-1-4799-8046-8
DOI :
10.1109/IADCC.2015.7154805
