Design of Vedic multiplier for high fault coverage and comparative analysis with conventional multipliers

Multipliers are the major contributors to the overall throughput in most SoCs. Vedic arithmetic is a novel and simplified approach to perform complex operations. Any good design must be targeted for optimal Speed-Area Trade-off. Commercial application demands reliable and economical design which makes testability an important parameter. Stuck-at-fault model for the design is to be developed and proper metrics have to be used to measure testability. Good design implies high fault coverage also. In this paper, design of Vedic multiplier with high fault coverage is proposed. Vedic multiplier designed using Urdhva-Triyagbhyam Sutra operates faster than the conventional multipliers like Booth and Array multipliers. Comparative analysis of VLSI parameters such as throughput, area and fault coverage is done with other multipliers.