Effect of increasing voltage levels on power saving obtained by multiple voltages design

Researchers believe that the power reduction at the earliest stages of the system design process will have higher impacts on the final result. Multiple supply voltage design is broadly acknowledged as a compelling approach to reduce the power consumption of a CMOS circuit. A SAT-based approach which targets operation scheduling with varying voltages and produces a circuit that consumes less power is proposed in this paper. Experiments with HLS benchmarks shows that the proposed schemes achieve more reduction in power once the number of operating voltage levels are increased (here 5v, 3.3v and 2.4v).