Optimised circuit configuration for STT-MTJ logic devices

In the array of 3D stackable non-volatile logic and memory devices, magnetic tunnel junction (MTJ) devices are most important due to their virtually unlimited endurance, fast read/write speed and low power consumption. These features render MTJs as an ideal candidate for realizing logic structures. An MTJ structure consists of two ferromagnetic layers separated by a thin, insulating spacer layer. The resistance of this MTJ structure can be remarkably tuned in changing the magnetic layers from a parallel to an anti-parallel state which can be used as logic “0” and logic “1”. Different approaches for switching one ferromagnetic layer have been introduced, namely the 2-termi-nal and 3-terminal MTJs. While 2-terminal cells can exploit spin transfer torque (STT) switching and have the advantage of scalability, 3-terminal MTJs employ domain wall motion (DWM) for writing operations and switching. In this work, we present a simplified circuit configuration based on a 5-terminal MTJ structure that is capable of NAND logic operations. This design greatly enhances the scalability by using only two MTJ structures to carry out logic operations.