Title :
A soft decodable concatenated LDPC code
Author :
Yang, S. ; Han, Y. ; Wu, X. ; Wood, R. ; Galbraith, R.
Author_Institution :
Avago Technol., San Jose, CA, USA
Abstract :
Low density parity check (LDPC) codes with iterative soft decoding have been adopted as the primary error correction coding technology in data storage devices, e.g., hard disk drives (HDDs) and solid state drives (SSDs). Data storage normally has stringent requirements for low probability of decoding failure since there is no re-transmission mechanism as available for most other data communication applications. Typically the error floor of a LDPC decoder in a storage application should be below 10-12. Recently, the adoption of 4 kB sector formats has allowed LDPC code word size to increase from 4096 user bits to 32768 user bits. This increase in code word size has enabled significantly more error correction power and better noise tolerance margin. Further increases in LDPC code block size beyond 4KB are expected to deliver further SNR gain but would be very expensive in terms of silicon area and power consumption.
Keywords :
error correction codes; iterative decoding; parity check codes; LDPC code block size; LDPC code word size; SNR gain; data storage devices; decoding failure; error correction power; error floor; hard disk drives; iterative soft decoding; low density parity check codes; noise tolerance margin; power consumption; primary error correction coding technology; silicon area; soft decodable concatenated LDPC code; solid state drives; Channel coding; Concatenated codes; Decoding; Error correction codes; Iterative decoding;
Conference_Titel :
Magnetics Conference (INTERMAG), 2015 IEEE
Conference_Location :
Beijing
Print_ISBN :
978-1-4799-7321-7
DOI :
10.1109/INTMAG.2015.7157702