Evolution of nanoscale silicon CMOS technology for ultra low power application

Author

Matsukawa, T. ; Morita, Y. ; Mori, T. ; Liu, Y.X. ; O´uchi, S. ; Migita, S. ; Masahara, M.

Author_Institution

Nanoelectron. Res. Inst., Nat. Inst. of Adv. Sci. & Technol. (AIST), Tsukuba, Japan

fYear

2015

fDate

4-5 June 2015

Firstpage

102

Lastpage

103

Abstract

Nanoscale silicon CMOS technology aimed for ultra low power application is presented. The characteristics variability and noise of FinFETs are dramatically suppressed by introducing an amorphous metal gate, and the suppression is beneficial both for scaling and reduction of power consumption. A tunnel FET (TFET) is also promising candidate to reduce the power consumption dramatically. The current drivability of a silicon TFET is improved significantly by introduction of a fin-type 3D structure and novel trap engineering.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; field effect transistor circuits; low-power electronics; silicon; FinFET noise; Si; amorphous metal gate; characteristics variability; fin-type 3D structure; nanoscale silicon CMOS technology; power consumption reduction; power consumption scaling; silicon TFET; trap engineering; ultra low power application; CMOS integrated circuits; CMOS technology; FinFETs; Metals; Silicon; Very large scale integration; FinFET; isoelectron trap; low frequency noise; tunnel FET; variavility;

fLanguage

English

Publisher

ieee

Conference_Titel

Future of Electron Devices, Kansai (IMFEDK), 2015 IEEE International Meeting for

Conference_Location

Kyoto

Print_ISBN

978-1-4799-8614-9

Type

conf

DOI

10.1109/IMFEDK.2015.7158570

Filename

7158570