Design and implementation of low-oversampling delta sigma modulators for high frequency applications

The key factor making Delta-Sigma modulators (DSM) one of the most popular components in modern electronic circuits is its high linearity. This is achieved by using a high oversampling ratio which is unfortunately the limiting factor towards its application in high frequency circuits. The necessity of high processing speed and power, the increased cost and complexity and wastage of available bandwidth are some of the significant demerits of using a high oversampling ratio. This paper suggests that the delta sigma modulators require a high frequency processing and not high oversampling ratio. A parallel structure to perform the high frequency processing along with an adaptive method to improve the signal quality at the output is proposed. The suggested technique allows the simultaneous execution of fast and complex computations required for wireless systems. The analysis is performed using MATLAB simulations and the results claim a reduction in oversampling ratio by a factor of 16 while keeping the same signal to noise ratio. The proposed architecture is implemented on a field-programmable gate array (FPGA) board which is then validated with a code division multiple access signal. The output signal bandwidth is observed to be increasing four times without any increase in the sampling frequency.